The present invention relates to a technique for manufacturing a semiconductor integrated circuit device, particularly a technique effective in application to a semiconductor integrated circuit device which uses a fuse of polysilicon to repair memory cell defects or make a fine adjustment of a semiconductor chip internal voltage.
Such semiconductor memories as a static random access memory (SRAM) and a dynamic random access memory (DRAM) are each provided with a redundancy circuit for repairing defects of some memory cells which occur in the memory manufacturing process. Switching from a defective memory cell to a spare memory cell formed in the redundancy circuit is usually performed by cutting a fuse of polysilicon. As to SRAM, it is described, for example, in U.S. Pat. No. 5,239,196 from Ser. No. 653,493 filed by the applicant in the present case on Feb. 11, 1991.
Further, the technique of providing an anti-reflection film for diminishing reflection from a base layer of resist at the time of patterning an aluminum wiring line using dry etching under the tendency to making the pattern size finer, is described, for example, in Nikkei Microdevice (published by Nikkei BP Co.) 1989 March Number, pp. 70-74. According to this literature, TiN is used on A1 as an anti-reflection film in SRAM.
By providing such anti-reflection film, it is possible to form a finish pattern as designed and hence possible to make the wiring pattern size finer.
As to the anti-reflection film, it is also described in U.S. Pat. No. 4,910,122.
Reference will now be made to an example of a manufacturing (first manufacturing process) for a semiconductor memory provided with a fuse which technique has not been regarded as well known but has been studied by the present inventor. FIGS. 37 to 44 are each a sectional view of a principal portion of a semiconductor substrate (wafer), in which the right-hand side represents a fuse forming region, the central portion represents a bonding pad forming region and the left-hand side represents a wiring forming region.
First, as shown in FIG. 37A, top wiring layers 200b and 200a are successively laminated onto an interlayer insulating film 105 of a semiconductor substrate 101. For example, the wiring layer 200b is an aluminum alloy film, while the wiring layer 200a is an anti-reflection film constituted by titanium-tungsten (TiW) or titanium nitride (TIN). Both films are formed by a sputter deposition method for example. Thus, the top wiring layer is of a multilayer structure of metallic films, whose top is formed by the anti-reflection film. For example, the top wiring layer is a second metallic wiring layer.
Next, as shown in FIG. 38B, the top wiring layer is subjected to patterning according to a dry etching method using photoresist 220 to form a top wiring line 200 and a bonding pad BP'.
On the other hand, a polysilicon fuse 106 is disposed below interlayer insulating films 103, 104 and 105 because it is formed simultaneously with the formation of a gate electrode of MOSFET (Metal-Oxide-Insulator Field Effect Transistor). In this example, the interlayer insulating film 103 is constituted by a silicon oxide film, the interlayer insulating film 104 is constituted by a BPSG (Boron-doped Phospho Silicate Glass) film, and the interlayer insulating film 105 is constituted by a three-layer insulating film comprising silicon oxide film, spin on glass (SOG) film and silicon oxide film which are successively laminated together. The top wiring line 200 is connected an underlying writing layer 210 through a through hole TH. The wiring layer 210 is a first metallic wiring layer.
Then, as shown in FIG. 38, a silicon oxide film 107 which constitutes a part of a final passivation film is deposited on the interlayer insulating film 105. The silicon oxide film 107 is deposited to a thickness of, say, 400 nm or so.
Next, as shown in FIG. 39, by etching the silicon oxide film 107, a bonding pad BP is exposed and an aperture 108 is formed above the fuse 106. Then, a probe (not shown) is applied to the surface of the bonding pad BP and a first electrical test is conducted. In the first electrical test, the device is checked mainly for its low temperature characteristic. When a defective memory cell was found out as a result of this test, a laser beam is radiated to the fuse 106 through the interlayer insulating films 105, 104 and 103 located below the aperture 108 to cut the fuse 106, thereby switching from the defective memory cell to a spare memory cell.
In the step of exposing the bonding pad BP shown in FIG. 39, the anti-reflection film 200a formed on the bonding pad BP' is removed together with the interlayer insulating film 107 by etching, using a photoresist 230.
The reason for removal of the anti-reflection film 200a formed on the bonding pad BP' is as follows. In the first electrical test, light is directed to the bonding pad BP and the reflected light is detected to thereby detect the position of the pad BP, and after alignment, a probe is applied to the pad BP. In this case, if the anti-reflection film 200a is present on the bonding pad BP, the reflected light from the same pad will be weakened, thus making it impossible to detect the position of the bonding pad. Therefore, it is necessary to remove the anti-reflection film 200a on the bonding pad.
Next, as shown in FIG. 40, a silicon oxide film 107' is again deposited on the silicon oxide film 107 to cover the bonding pad BP and the aperture 108, and a silicon nitride film 109 is deposited thereon. Together with the underlying silicon oxide films 107 and 107' the silicon nitride film 109 constitutes a final passivation film. In this case, the silicon oxide film 107' is deposited at a thickness of, say, 400 nm or so by a plasma CVD (chemical vapor deposition) method for example, and the silicon nitride film 109 is deposited at a thickness of, say, 1.2 .mu.m or so also by the plasma CVD method. As a result of the deposition of both films 107' and 109, the aperture 108 located above the fuse 106 is filled up by the final passivation film. Consequently, it is possible to prevent the occurrence of corrosion near the fuse 106 which is caused by the entry of moisture from the air through the aperture 108 after cutting of the fuse.
Then, as shown in FIG. 41, the silicon oxide film 107' is exposed by etching the silicon nitride film 109 positioned above the bonding pad BP, using a photoresist 240 as mask, and thereafter a polyimide resin 110 is applied onto the silicon nitride film 109, as shown in FIG. 4. The application of the polyimide resin 110 is made so as to give a film thickness of, say, 10 .mu.m or so.
Next, as shown in FIG. 43, the silicon nitride film 109 and the silicon oxide film 107' are exposed by etching the polyimide resin 110 positioned above the bonding pad BP, using a photoresist 250 as mask. Further, after removal of the photoresist 250, the bonding pad BP is exposed by etching the silicon oxide film 107' using the silicon nitride film 109 as mask, as shown in FIG. 44. Thus, in this etching step, the silicon oxide film is removed selectively by using an etchant which exhibits a high selection ratio between silicon nitride film and silicon oxide film.
Next, there is performed the second electrical test in which the probe is applied to the surface of the bonding pad BP. In the second electrical test, the device is checked mainly for its high-temperature characteristic. By this test it is judged whether each chip on the semiconductor wafer is good or bad. In this way the semiconductor memory manufacturing process (wafer process) is completed.
Thus, in the above technique, the reliability of the fuse cutting aperture is ensured by coating the aperture completely with a final passivation film while keeping the increase in the number of manufacturing steps to a minimum.
However, since the manufacturing process involves a step of depositing the final passivation film (comprising silicon oxide film and silicon nitride film) during the period after the first electrical test until the second electrical test, it is likely that the device characteristics will be changed due to thermal damage, charge-up or any other heat treatment in the final passivation film depositing step and that a chip which was judged to be good in the first electrical test will become defective while going through subsequent steps.
Particularly, in connection with the SRAM described in the foregoing U.S. Pat. No. 5,236,196, the present inventor found out that there was a fear of change in device characteristics, e.g. Vth shift or decrease of Ids, in a p-channel load MISFET constituted by a polysilicon film formed on a driver MISFET.
For the purpose of avoiding the above-mentioned inconvenience, there has been proposed the following manufacturing process (second manufacturing process) shown in FIGS. 45 to 51A and not involving a step which causes a thermal damage between the first and second electrical tests.
First, as shown in FIG. 45A, top wiring layers 200b and 200a are successively laminated onto a semiconductor substrate 101 in the same manner as in the foregoing manufacturing process shown in FIG. 37A, [step (a) in FIG. 51A].
Next, as shown in FIG. 45B, a top wiring line 200 and a bonding pad BP' are formed in the same manner as in the foregoing manufacturing process shown in FIG. 37B, [step (b) in FIG. 51A].
Then, as shown in FIG. 45C, the other portion than a bonding pad forming region is covered with a photoresist (not shown), and only the anti-reflection film 200a on the bonding pad BP' is removed by etching, [step (c) in FIG. 51A].
On the other hand, by allowing the anti-reflection film 200a to remain in the top wiring line 200 except the portion corresponding to the bonding pad BP, it is made possible to diminish the occurrence of breaking of the wiring line 200 caused by electromigration, etc. Such a technique of providing an anti-reflection film (TIN) as a top layer in a multilayer structure of metallic films and diminishing electromigration is described in IEEE Transactions on Electron Devices, Vol. 40, No. 2, February 1993, pp.296-302.
Next, as shown in FIG. 46, a final passivation film (comprising silicon oxide film 107 and silicon nitride film 109) is deposited on an interlayer insulating film 105, [steps (d) and (e) in FIG. 51A]. The silicon oxide film is deposited at a thickness t.sub.1 of 800 nm or so. Thus, in this manufacturing process, a thickness of about 800 nm is obtained at a time although in the foregoing first manufacturing process the silicone oxide film 107 was deposited in two stages each about 400 nm in thickness. The silicon nitride film 109 is deposited at a thickness of about 1.2 .mu.m which is the same as in the first manufacturing process.
Then, as shown in FIG. 47, the silicon nitride film 109 above the bonding pad BP and that above a fuse 106 are etched using a photoresist 260 as mask to expose the silicon oxide film 107. Thereafter, the resist 260 is removed, and a polyimide resin 110 is applied onto the silicon nitride film 109, as shown in FIG. 48. In this case, the thickness of the resulting polyimide film is set at about 10 .mu.m which is the same as in the first manufacturing process.
Next, as shown in FIG. 49, the polyimide resin 110 above the bonding pad BP and that above the fuse 106 are etched using a photoresist 270 as mask to expose the silicon nitride film 109 and the silicon oxide film 107, followed by removal of the resist 270. Then, as shown in FIG. 50, by etching the silicon oxide film 107 using the silicon nitride film 109 as mask, the bonding pad BP is exposed and at the same time an aperture 108 is formed above the fuse 106.
Next, the first electrical test is made while applying a probe to the surface of the bonding pad BP. When a defective memory cell was found out in this first electrical test, a laser beam is radiated to the fuse 106 through the interlayer insulating films 105, 104 and 103 located below the aperture 108 to cut the fuse, thereby switching from the defective memory cell to a spare memory cell.
Subsequently, there is conducted the second electrical test while applying the probe to the surface of the bonding pad BP. By this electrical test it is judged whether each chip on the semiconductor wafer is good or bad, and the semiconductor manufacturing process (wafer process) is completed.
Thus, in the second manufacturing process described above, two electrical tests and memory cell defect repair are performed continuously in the final stage of the wafer process. Unlike the first manufacturing process, therefore, there is no fear of change in device characteristics between the first and the second electrical test, so that it is possible to judge exactly whether a semiconductor chip is good or bad.